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BD6088GUL
● Timing diagram
SDA
t BUF
Technical Note
SCL
t LOW
t SU;DAT
t HD;STA
t HD;STA
t HD;DAT
t SU;STA
t SU;STO
S
t HIGH
Sr
P
S
● Electrical Characteristics(Unless otherwise specified, Ta=25 o C, VBAT=3.6V, VIO=2.6V)
Standard-mode
Fast-mode
Parameter
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
【 I 2 C BUS format 】
SCL clock frequency
LOW period of the SCL clock
HIGH period of the SCL clock
Hold time (repeated) START condition
After this period, the first clock is generated
Set-up time for a repeated START condition
Data hold time
Data set-up time
Set-up time for STOP condition
Bus free time between a STOP and START
condition
f SCL
t LOW
t HIGH
t HD;STA
t SU;STA
t HD;DAT
t SU;DAT
t SU;STO
t BUF
0
4.7
4.0
4.0
4.7
0
250
4.0
4.7
-
-
-
-
-
-
-
-
-
100
-
-
-
-
3.45
-
-
-
0
1.3
0.6
0.6
0.6
0
100
0.6
1.3
-
-
-
-
-
-
-
-
-
400
-
-
-
-
0.9
-
-
-
kHz
μ s
μ s
μ s
μ s
μ s
ns
μ s
μ s
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? 2011 ROHM Co., Ltd. All rights reserved.
12/51
2011.04 - Rev.A
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